Tag Archives: Xilinx

Udemy Learning and FPGA Development

I recently signed up with Udemy which claims to be the world’s largest destination for on-line courses. A rather tall order and time will tell. However they do have a huge selection of courses available covering everything from programming to break dancing!! Some of courses are rather expensive but they regularly offer special promotional rates on a lot of these courses that does make them more attractive.

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I have just completed my first course a course created by a reader of this blog by the name of Jordan Christman. Jordan’s course entitled “VHDL and FPGA Development for Beginners and Intermediates” is an excellent introduction to VHDL and FPGA development. Jordan introduces the basics of FPGAs and VHDL before moving onto the development tools used and then takes a hands on approach developing, simulating and running simple designs on target hardware platforms. I can thoroughly recommended this course to anyone wanting to get into FPGA development. Well done Jordan.

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Driving a 7 segment display

During my recent adventures in FPGAs I have been driving the 7 segment LED display on the LogicStart Megawing I recently purchased for my Paplilio One FPGA board. The board contains an array of 4 common anode 7 segment display characters. Four control lines are used to enable the digits while a further 8 lines are used to drive each segment (7 segments + dp). One thing I noticed while driving these displays was that the segments seemed brighter than expected and the digits were getting rather warm.

LogicStart Mega Wing

After a bit of searching I found the schematic diagram for the LogicStart Mega Wing. There appears to be some omissions on the board. Firstly there are no current limiting resistors on each of the individual segments. These are LEDs so the current needs to be limited to avoid damaging them. I assume the FPGAs internal resistance must be limiting the current somewhat but he fact the display is over heating means its drawing way too much. Secondly there are no current limiting resistors on base of the transistors used to switch power to each character. I could use PWM signal with a suitable duty cycle to lower average current but that’s a pain. Another option would be to add current limiting resistors which means butchering the board. I already had a red seven segment display an a few BC212s in my parts bin so I set about designing my own seven segment display wing.

I decided on a forward current of 10 mA through each segment. According to the Spartan 3 datasheet it is capable of sinking 24 mA per pin so 10 mA shouldn’t be an issue. The forward voltage of the LED is 1.9V and the supply voltage is 3.3V.

Rseries = (Vcc-Vf)/If = (3.3V-1.9V)/10mA = 140R. Nearest E12 value 150R.

With all eight segments illuminated the total current would be approx 80 mA. The DC current gain of the transistor according to the data sheet is a minimum of 60. Vbe(sat) = 1.4V @ 100 mA.

Ib = Ic/hfe = 80mA/60 = 1.34 mA. Rb = Vrb/Ib = (Vcc-Vbe(sat))/Ib = (3.3V-1.4V)/1.34mA = 1418R. Nearest E12 value = 1K5.

For robustness I added a few LEDs and a couple of switches to the board.

Getting started with FPGAs…Part 2

So it has been just over a week since I started my journey into FPGAs and so far so good. As a starting point I decided I would work my way through Mike Fields ebook Introducing the Spartan 3E FPGA and VHDL which I must say is an excellent resource and I thoroughly recommend it to anybody wanting to learn about FPGAs from a hands on point of view.

For the last week or so I have spent most of my lunch breaks working my way through the course. It begins with the basics, why choose FPGAs, what development tools etc and then moves quickly onto the hands on stuff like turning on LEDs, binary operations, using signals, clock sources, simulation and much more. Coming from an embedded software background I did find adapting my mindset to a non-procedural way of thinking a bit of a challenge.

Getting to grips with VHDL is fun though, I love the that a digital circuit may be fully realized in a descriptive programming language. What is great about this whole experience though is recalling all those digital electronics fundamentals that have been relegated to the back of my mind.

Below I have posted my attempt at one of the mini projects in Mikes guide. This project implements two up counters using separate 30 bit counter modules. The counters are enabled via an external signal (one of the switches on the LogicStart board) and are clocked via the Papilios 32MHz oscillator. The upper 4 bits of each counter are connected to LEDs on the LogicStart board.

Firstly the project file “Switches_LEDs_Counter.vhd”.

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity Switches_LEDs_Counter is  
   Port ( LEDs : out STD_LOGIC_VECTOR(7 downto 0);  
       Switches : in STD_LOGIC_VECTOR(1 downto 0);  
       clk : in STD_LOGIC  
       );  
 end Switches_LEDs_Counter;  
 architecture Behavioral of Switches_LEDs_Counter is  
 signal count1 : STD_LOGIC_VECTOR(29 downto 0)  := (others => '0');  
 signal count2 : STD_LOGIC_VECTOR(29 downto 0)  := (others => '0');  
 COMPONENT Counter30  
   PORT(  
     clk : IN std_logic;  
     enable : IN std_logic;  
     count : OUT std_logic_vector(29 downto 0)  
     );  
   END COMPONENT;  
 begin  
 LEDs(3 downto 0) <= count1(27 downto 24);  
 LEDs(7 downto 4) <= count2(27 downto 24);  
 Inst_Counter30_1: Counter30 PORT MAP(  
     clk => clk,  
     enable => Switches(0),  
     count => count1  
   );  
 Inst_Counter30_2: Counter30 PORT MAP(  
     clk => clk,  
     enable => Switches(1),  
     count => count2  
   );  
 end Behavioral;  

Secondly the 30 bit counter module “Switches_LEDs_Counter_Module.vhd”.

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 entity Counter30 is  
   Port ( clk : in STD_LOGIC;  
       enable : in STD_LOGIC;  
       count : out STD_LOGIC_VECTOR (29 downto 0));  
 end Counter30;  
 architecture Behavioral of Counter30 is  
 signal my_count : STD_LOGIC_VECTOR(29 downto 0) := (others => '0');  
 begin  
 count <= my_count;  
 clk_proc: process(clk)  
   begin  
     if rising_edge(clk) then  
       if enable = '1' then  
         my_count <= my_count+1;  
       else  
         my_count <= (others => '0');  
       end if;  
     end if;  
   end process;  
 end Behavioral;  

OK so its not some fancy all singing all dancing SDRAM controller but we all have to start somewhere right.

Getting started with FPGAs

Like a lot of engineers I was first exposed to FPGAs back in university. A number of years have since passed and most of the stuff I learnt I have since forgotten. At the time FPGAs were mysterious devices that cost a fortune and where insanely difficult to program. Fast forward some 10+ years and technology has moved on. These devices seem to be appearing more and more and not only in commercial products but in peoples personal endeavours as well. Development boards although still expensive when compared with those for micro controllers are coming down in price. So I decided it was high time I got myself a board and got up to speed.

Choosing a board wasn’t a simple task. Although the FPGA market appears to be dominated by two players Altera and Xilinx. Which to choose? For me it came down to the quality of the tools and support. Both offer free versions of their development tools but after reading numerous reviews, articles and blogs I had a slight leaning towards Xilinx. No particular reason I just felt their tools were a bit fresher, had less limitations and the support Xillinx provides appears to be first class.

After much deliberation I decided on the Papilio FPGA development board. The Papilio is an open source FPGA development board that comes in two flavours (technically its three). The Papilio One which contains a Spartan 3E FPGA (in 250K and 500K gate count) and the Papilio Pro which contains a Spartan 6 LX9 FPGA. Both boards are minimalistic in design.  The Papilio One in addition to the FPGA contains an on board power supply with selectable I/O voltage and two channel USB connection for JTAG and serial communications. The Papilio Pro also features an on board power supply, USB connection and an additional 64Mbit SDRAM.

Additional hardware maybe added in the form of wings. That way you can purchase wings to support the features you require and not be lumbered with things you don’t. This allows you to cut down on initial layout costs. Being open source the Papilio hardware has huge support in on-line forums.

The Paplio One 250K version is available from Gadget Factory for $37.99, the 500K version for $64.99 and the Papilio Pro is available for $84.99. Even when you take into account shipping costs and currency conversion these boards still represent excellent value for money.

Papilio One

I decided to order the Papilio One 500K version and the additional Logic Start mega wing. The Logic Start mega wing contains a 7 segment display, VGA port, mono audio jack, micro joystick, SPI ADC, 8 LEDs and 8 slide switches. Great for getting up and running and experimenting.

Just over a week later and the board arrived. Not bad considering this is coming all the way from the United States to the UK.

In the mean time I had already installed the Xilinx ISE Webpack development suite as well as downloading the “hello_word” bit file and the Papilio loader tool. The next stage was to brush up on my VHDL. I decided to start with VHDL as opposed Verilog since VHDL appears to be more popular in Europe than Verilog. Realistically a good FPGA engineer would be expected to be sufficiently competent in both VHDL and Verilog but everyone has to start somewhere.